The semester is over, but I thought I should post results from another final project. For ESE 570 at Penn, two fellow juniors and I implemented a 4-bit signed Wallace Tree multiplier in 0.6μm CMOS. The design uses two CSAs for reduction and an 8-bit ripple-carry adder to deliver the final product. In the end, 952 transistors were used for implementation, with layout dimensions of 253.95μm x 499.95μm (area of 0.127 square millimeters). I'm happy to say it passed all of our tests too, and had a propagation delay of 3.1 nanoseconds, which we didn't feel was too shabby given our time constraints. I'm sure we could do better if we spent the time to size transistors appropriately. An image of the layout is shown below.
Implementing digital logic at this level really gives some extra insight on all the bit arithmetic learned in freshman/sophomore-level digital design courses. Sign-extension and shifting really are just dragging the wires around (and maybe a little bit of buffering). I can now say that I have some Cadence experience too. phew...
